1. Field of the Invention
The present invention relates generally to semiconductor memory devices and more particularly, to semiconductor memory devices in which writing is inhibited in an address skew period and controlling method thereof.
2. Description of the Prior Art
FIG. 1 is a block diagram showing schematic structure of an example of a conventional static random access memory (referred to as SRAM hereinafter).
A memory cell array 1 comprises a plurality of word lines, a plurality of bit line pairs arranged intersecting with the plurality of word lines, and a plurality of memory cells each arranged at each of intersections thereof. The word lines are connected to an X decoder 3 and the bit line pairs are connected to a Y decoder 5. An X address buffer 2 applies an address signal AX comprising a plurality of address signals externally applied, as an address signal ax, to the X decoder 3 and an address transition detector 20. The X decoder 3 is responsive to the address signal ax applied from the X address buffer 2 for selecting one of the plurality of word lines. A Y address buffer 4 applies an address signal AY comprising a plurality of address signals externally applied, an address signal ay, to the Y decoder 5 and the address transition detector 20. The Y decoder 5 is responsive to the Y address signal ay applied from the Y address buffer 4 for selecting one of the plurality of bit line pairs. Data is read out or written from or to a memory cell at an intersection of the selected word line and the selected bit line pair. A read/write control circuit 10 operates a read circuit 6 when a write enable signal WE is at an "H" level while operating a write circuit 8 when the write enable signal WE is at an "L" level. At the time of reading out data, the data stored in the memory cell selected in the above described manner is outputted through a data output buffer 7 by the read circuit 6. At the time of writing data, data externally applied to a data input buffer 9 is inputted to the memory cell selected in the above described manner by the write circuit 8.
The address transition detector 20 detects the change of the address signals ax and ay to generate a detection signal GATD. The detection signal GATD is applied to the memory cell array 1 as an equalize signal BLEQ.
FIG. 2A is a circuit diagram showing structure of the memory cell array 1 shown in FIG. 1, and FIG. 2B is a circuit diagram showing a memory cell included in the memory cell array 1.
In FIG. 2A, a plurality of word lines WL are arranged in the memory cell array 1, a plurality of bit line pairs BL and BL being arranged intersecting therewith. A memory cell MC is provided at each of intersections of the plurality of word lines WL and the plurality of bit line pairs BL and BL. The plurality of word lines WL are connected to the X decoder 3. The bit lines BL and BL are connected to a power-supply potential through bit line load constituting N channel MOSFETs Q6 and Q7, respectively. An equalizing N channel MOSFET Q5 is connected between the bit lines BL and BL. The equalizing N channel MOSFET Q5 has its gate coupled to an equalize signal BLEQ. The bit lines BL and BL are connected to a pair of input/output lines I/O and I/O through N channel MOSFETs Q8 and Q9, respectively. The MOSFETs Q8 and Q9 have their gates connected to the Y decoder 5. A set of MOSFETs Q8 and Q9 is turned on by the Y decoder 5, so that data on the bit line pair BL and BL connected to the MOSFETs Q8 and Q9 are read out to the input/output lines I/O and I/O. The potential difference between the input/output lines I/O and I/O is amplified by a sense amplifier SA and outputted through a data bus DB and a buffer BF. An equalizing N channel MOSFET Q10 is connected between the input/output lines I/O and I/O. The equalizing N channel MOSFET Q10 has its gate coupled to an equalize signal IOEQ. The MOSFETs Q5 and Q10 are turned on in response to the equalize signals BLEQ and IOEQ before reading out or writing data, so that potentials of the bit lines BL and BL and potentials of the input/output lines I/O and I/O are equalized, respectively. The equalize signals BLEQ and IOEQ are the same signals as the detection signal GATD from the address transition detector 20 or signals obtained by waveform-shaping the detection signal GATD.
A precharging circuit 11 is connected to the data bus DB. The precharging circuit 11 is responsive to a precharging signal PR for precharging the data bus DB to an intermediate potential between the "H" level and the "L" level. The precharging signal PR is the detection signal GATD or a signal obtained by waveform-shaping the detection signal GATD, similarly to the equalize signals BLEQ and IOEQ.
In FIG. 2B, a memory cell MC includes N channel MOSFETs Q1 to Q4 and resistances R1 and R2. The resistance R1 is coupled between the power-supply potential and a node n1, the resistance R2 is coupled between the power-supply potential and a node n2. The MOSFET Q1 is coupled between the node n1 and a ground potential, and has its gate connected to the node n2. The MOSFET Q2 is coupled between the node n2 and the ground potential, and has its gate connected to the node n1. The MOSFET Q3 is connected between the node n1 and the bit line BL, and has its gate connected to the word line WL. The MOSFET Q4 is connected between the node n2 and the bit line BL, and has its gate connected to the word line WL.
Complementary data are stored in the nodes n1 and n2. When a potential of the word line WL attains the "H" level, the MOSFETs Q3 and Q4 are turned on. As a result, at the time of a read operation, the data stored in the nodes n1 and n2 are read out to the bit lines BL and BL, respectively. On the other hand, at the time of a write operation, the data on the bit lines BL and BL are written to the nodes n1 and n2, respectively.
FIG. 2C is a block diagram showing structure of the address transition detector 20 shown in FIG. 1.
A plurality of ATD pulse generators 201 are provided corresponding to a plurality of address signals A1 to An included in the address signals ax and ay. The ATD pulse generators 201 are responsive to the change of the address signals A1 to An for generating one-shot pulses ATD1 to ATDn, respectively. An OR circuit 202 ORs outputs of the ATD pulse generators 201, to output the same as the detection signal GATD. The detection signal GATD may be obtained by ORing signals waveform-shaped by a buffer.
FIG. 3 is a waveform diagram showing the operation timing of the X address buffer 2, the X decoder 3, the Y address buffer 4 and the Y decoder 5.
When the address signal AX changes, the address signal ax outputted from the X address buffer 2 responsively changes. An output of the X decoder 3 also changes in response to the change of the address signal ax, so that another word line is selected. On this occasion, a one-shot pulse ATD is generated in the address transition detector 20 in response to the change of the address signal ax. In the same manner, when the address signal AY changes, the address signal ay outputted from the Y address buffer 4 responsively changes. An output of the Y decoder 5 changes in response to the change of the address signal ay, so that another bit line pair is selected. On this occasion, a one-shot pulse ATD is generated in the address transition detector 20 in response to the change of the address signal ay.
FIG. 4 is a waveform diagram showing an example of the timing for writing in the above described SRAM.
It is assumed that two address signals A1 and A2, of a plurality of address signals included in the address signal ax and ay change. After the address signals A1 and A2 change, the write enable signal WE falls to the "L" level, so that a write operation is performed. In the period during which the write enable signal WE is at the "L" level, data is written to the selected memory cell, so that data at the rise time point tw of the write enable signal WE remains in the memory cell.
Meanwhile, the address signal includes address skew represented by a period t1, and the write enable signal WE includes jitter represented by periods t3 and t4. Address skew means a shift of timing of the change of a plurality of address signals depending on the system precision when the address signals change. t3 is the maximum value of a jitter period at the time of the change of the write enable signal WE from the "H" level to the "L" level, and t4 is the maximum value of a jitter period at the time of the change of the write enable signal WE from the "L" level to the "H" level. Jitter means that a signal changes irregularly. Thus, in practice, when the SRAM is carried on a board to be employed as a system, a cycle time Tc of the system becomes as follows, even if the address setup time t5 and the write recovery time t6 which are specification values of the SRAM are assumed to be 0 ns, respectively; EQU Tc=t1+t3+t2+t4
where t2 denotes a write pulse width which is a specification value of the SRAM. In particular, in the SRAM which operates at very high speed, the ratio of the jitter periods t3 and t4 to the cycle time Tc is increased. The high speed characteristic is lost due to the jitter periods t3 and t4.
When data is written with the write enable signal WE being fixed in advance at the "L" level, i.e., in a write state, the jitter periods t3 and t4 can be also neglected. If this method is used, data stored in a memory cell selected transiently in the address skew period t1 may be reloaded. For example, in FIG. 4, data can be written to a memory cell selected by the address signal A1 after change and the address signal A2 before change in the address skew period t1.
One solution to this problem includes a method in which the change of address signal is detected to generate a one-shot pulse ATD and a write operation in a chip is inhibited by using the pulse. FIG. 5 illustrates the operation timing of the SRAM using this method.
In the SRAM using this method, the same signal as the detection signal GATD of the address transition detector 20 is applied to the read/write control circuit 10 as a write inhibiting signal WI as shown in FIG. 1.
In FIG. 5, address skew represented by the period t1 occurs between the address signals A1 and A2. The write enable signal WE has been fixed at the "L" level before the change of address signal. In the address transition detector 20, a one-shot pulse ATD1 is generated in response to the change of the address signal A1, and a one-shot pulse ATD2 is generated in response to the change of the address signal A2. The address transition detector 20 outputs a detection signal GATD obtained by ORing the one-shot pulses ATD1 and ATD2. The same signal as the detection signal GATD is applied to the equalizing transistor Q5 (in FIG. 2A) in the memory cell array 1 as an equalize signal BLEQ, as well as to the read/write control circuit 10 as a write inhibiting signal WI. Although in FIG. 1, the equalize signal BLEQ and the write inhibiting signal WI are almost the same as the detection signal GATD, the signals may be signals obtained by waveform-shaping and increasing the driving ability, or the like of the detection signal GATD by using a buffer or the like. The read/write control circuit 10 applies to the write circuit 8 an internal write signal WE obtained by inverting the write inhibiting signal WI. A write operation is inhibited when the internal write signal WE is at the "L" level while being performed when it is at the "H" level. Thus, in the address skew period t1, the write operation is inhibited, so that data stored in a memory cell selected transiently in the period t1 can be prevented from being destroyed.
However, as shown in FIG. 6, if an address skew period t1' is longer (t1'&gt;t1), the period at the "H" level of the detection signal GATD obtained by the one-shot pulses ATD1 and ATD2 is divided into two, so that the period t7 at the "L" level appears during the period at the "H" level. As a result, the period at the "H" level of the internal write signal WE appears in the address skew period t1', so that data is erroneously written to a memory cell transiently selected. Consequently, data stored in the memory cell may be destroyed.
In order to solve this problem, it is considered that in the address transition detector 20, the one-shot pulse ATD having a large width or the detection signal GATD having a large width is adapted to be generated. However, if the detection signal GATD is long, the width of the equalize signal BLEQ is increased, so that access times in the SRAM become slow.